AI-Native Chip Design Infrastructure
Autonomous infrastructure for analog, RF & mixed-signal chip design.
We build the runtime, tooling, and IP that take analog and RF chip design from manual iteration to autonomous loops.
Analog, RF, and mixed-signal design is still done by hand. Closure verdicts depend on engineer intuition; obligations drift across runs; process migrations break things silently; provenance lives in spreadsheets and tribal knowledge. Nectrion's wedge is the boring part: make every design step a typed artifact, every simulator interaction a typed adapter, every closure mechanically computed, and every run replayable.
Analog / RF closure. Mechanically computed, not narrated.
Replayability. Every run reconstructable end-to-end.
PDK & tool integration. One typed surface across the stack.
IP provenance. Blocks carry their obligations and history.
What we build
One runtime, three offerings.
Everything we sell sits on the same artifact-first runtime. Services validate it on real customer designs, the IP library compounds the engineering output, and the fabless product path is how we anchor on India's structural demand.
Runtime
The design engine
Typed-artifact runtime with a Pydantic-validated schema layer, replay-safe execution, provenance and credentialing, multi-PDK abstraction, and an intent-graph closure model.
Design services
Analog & RF design partners
Fixed-scope analog and RF design engagements for semiconductor teams that need a partner who can move fast on closure and integrate cleanly with their existing flow.
IP library
Silicon-oriented IP blocks
A growing catalog of analog and RF building blocks delivered with the same provenance, replay, and obligation tracking as the runtime that built them.
Products
Fabless product path
Nectrion-branded silicon for high-volume Indian anchor markets, built on the same runtime and IP library that powers the services and licensing pillars.
Who we serve
Built for teams across the Indian and global analog stack.
Nectrion is built to serve teams that ship analog and RF silicon — whether the chip is a smart-meter AFE, an EV battery monitor, an RF front-end, or a defense radar subsystem. We work with OEMs, SoC integrators, and fabless teams.
Smart metering
Energy & metering OEMs
AFEs, signal-chain blocks, and integrated solutions for India's smart-meter rollout and adjacent industrial metering markets.
Defense
Defense & aerospace
RF and mixed-signal subsystems with the provenance, replayability, and audit trail that defense procurement actually requires.
Auto / EV
Automotive & EV
Battery management, motor control, on-board charger analog and mixed-signal blocks for India's EV and Tier-1 automotive ecosystem.
Telecom
Telecom & 5G
RF front-end and mixed-signal infrastructure for telecom equipment, base-station, and CPE customers building on Indian and partner foundries.
Fabless teams
Fabless & design houses
Analog and RF design partnerships for global mid-tier fabless companies that need fast turnaround without spinning up a full internal analog team.
Engineering surface
What's actually inside the runtime.
For customer engineers and prospective hires: the technical surface is concrete, typed, and verifiable. We integrate with the tools you already use, and we treat every artifact in the pipeline as a first-class object.
Typed runtime
Artifacts, not free-form data
Pydantic-validated schemas at every runtime hand-off.
Adapter layer
EDA & simulator integrations
Typed integrations across the open and commercial EDA stack.
PDK posture
Multi-PDK by design
Registry, resolver, and emitter layer abstract PDK details out of the design loop.
Closure model
Intent graph & replay bundles
Typed obligations, mechanically computed closure, every run replayable.
Careers
Build the runtime and the IP that ships on it.
We're hiring senior analog and RF engineers, AI/ML engineers focused on optimization and surrogate modeling, and runtime/infrastructure engineers comfortable with typed systems. The bar is high; the work is concrete; the work targets real silicon.
Email careers- Senior analog / RF engineerClosure-driven, replay-safe loops on real silicon.
- AI / ML engineer (chip design)Optimization, surrogate models, retrieval, evaluation harness.
- Runtime / infrastructure engineerTyped Python, Pydantic, replay, provenance, EDA adapters.
Contact
Three lanes, one inbox.
Whatever you're reaching out about, the email is the same. The subject line tells us who you are so we can route quickly.
Customers & partners
Talk to our team
For semiconductor teams, OEMs, SoC integrators, fabless companies, and foundry / packaging partners.
Email the teamCareers
Join us
For senior analog, RF, AI/ML, and infrastructure engineers. Send a short note and a CV or links to your work.
Email careersInvestors
Investor relations
For inbound investor outreach. We respond with a deck and a runtime walkthrough on request.
Email investor relations